CS4354-CSZ【PDF 12/24 页】IC DAC 24BIT SRL 14SOIC

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Sheet目录1991

8页 9页 10页 11页 [12页]13页 14页 15页 16页

DS895F2

CS4354

TABLE OF CONTENTS

1. PIN DESCRIPTIONS

........................................................................................................................... 4

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5

RECOMMENDED OPERATING CONDITIONS .................................................................................... 5

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5

DAC ANALOG CHARACTERISTICS .................................................................................................... 6

COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS ................................... 7

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ......................................................... 8

DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 10

INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 10

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 11

2.1 Digital I/O Pin Characteristics ........................................................................................................ 11

3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12

4. APPLICATIONS ................................................................................................................................... 13

4.1 Ground-Centered Line Outputs ...................................................................................................... 13

4.2 Sample Rate Range/Operational Mode Detect .............................................................................. 13

4.3 System Clocking ............................................................................................................................ 13

4.4 Serial Clock .................................................................................................................................... 14

4.4.1 External Serial Clock Mode ................................................................................................... 14

4.4.2 Internal Serial Clock Mode .................................................................................................... 14

4.4.2.1 De-Emphasis Control ................................................................................................. 14

4.5 Internal High-Pass Filter ................................................................................................................ 15

4.6 Digital Interface Format .................................................................................................................. 15

4.7 Internal Power-On Reset ............................................................................................................... 15

4.8 Initialization .................................................................................................................................... 16

4.9 Recommended Operational Sequences ........................................................................................ 18

4.9.1 Power-Up .............................................................................................................................. 18

4.9.2 Power-Down .......................................................................................................................... 18

4.9.3 Sample Rate Change ............................................................................................................ 18

4.10 Grounding and Power Supply Arrangements .............................................................................. 18

4.10.1 Capacitor Placement ........................................................................................................... 19

5. COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE PLOTS

.............................. 20

6. PARAMETER DEFINITIONS ................................................................................................................ 22

7. PACKAGE INFORMATION .................................................................................................................. 23

7.1 Dimensions .................................................................................................................................... 23

7.2 Thermal Characteristics ................................................................................................................. 23

8. ORDERING INFORMATION ................................................................................................................ 23

9. REVISION HISTORY ............................................................................................................................ 24

LIST OF FIGURES

Figure 1. External Serial Clock Mode Input Timing ..................................................................................... 9

Figure 2. Internal Serial Clock Mode Input Timing ...................................................................................... 9

Figure 3. Internal Serial Clock Generation .................................................................................................. 9

Figure 4. Power-On Reset Threshold Sequence ...................................................................................... 10

Figure 5. Typical Connection Diagram ...................................................................................................... 12

Figure 6. CS4354 Data Format (IS) ......................................................................................................... 14

Figure 7. De-Emphasis Curve, Fs = 44.1 kHz .......................................................................................... 15

Figure 8. Internal Power-On Reset Circuit ................................................................................................ 15

Figure 9. Initialization and Power-Down Sequence Diagram .................................................................... 17

Figure 10. Single-Speed Stopband Rejection ........................................................................................... 20

Figure 11. Single-Speed Transition Band ................................................................................................. 20

Figure 12. Single-Speed Transition Band (detail) ..................................................................................... 20

Figure 13. Single-Speed Passband Ripple ............................................................................................... 20

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